The fabrication of integrated circuits from silicon or other wafers involves many steps of depositing layers, photo lithographically patterning the layers, and etching the patterned layers. Ion implantation is used to dope active regions in the semiconductive silicon. The fabrication sequence also includes thermal annealing of the wafers for many uses including curing implant damage and activating the dopants, crystallization, thermal oxidation and nitridation, silicidation, chemical vapor deposition, vapor phase doping, thermal cleaning, and other reasons. Although annealing in early stages of silicon technology typically involved heating multiple wafers for long periods in an annealing oven, rapid thermal processing, (RTP) has been increasingly used to satisfy the ever more stringent requirements for ever smaller circuit features. RTP is typically performed in single-wafer chambers by irradiating a wafer with light from an array of high-intensity lamps directed at the front face of the wafer on which the integrated circuits are being formed. The radiation is at least partially absorbed by the wafer and quickly heats it to a desired high temperature, for example above 600° C., or in some applications, above 1000° C. The radiant heating can be quickly turned on and off to controllably heat the wafer over a relatively short period, for example, of a minute or less, or even a few seconds.
FIG. 1 schematically represents a Radiance RTP reactor 10, available from Applied Materials, Inc. of Santa Clara, Calif. Peuse et al. describe further details of this type of reactor and its instrumentation in U.S. Pat. Nos. 5,848,842 and 6,179,466, all incorporated herein by reference in their entireties. A wafer 12 to be thermally processed is supported on its periphery by an edge ring 14 having an annular sloping shelf 15 contacting the corner of the wafer 12. The size of wafers is currently transitioning from 200 mm to 300 mm in diameter. Ballance et al. more completely describe the edge ring and its support function in U.S. Pat. No. 6,395,363, incorporated herein by reference in its entirety. The wafer is oriented such that processed features 16 already formed in a front surface of the wafer 12 face upwardly, referenced to the downward gravitational field, toward a process area 18 defined on its upper side by a transparent quartz window 20. Contrary to the schematic illustration, the features 16 for the most part do not project substantial distances beyond the surface of the wafer 12 but constitute patterning within and near the plane of the surface. The nature of the wafer features 16 is multi-faceted and will be discussed later. Three lift pins 22 may be raised and lowered to support the back side of the wafer 12 when the wafer is handed between a paddle bringing the wafer into the chamber and the edge ring 14. A radiant heating apparatus 24 is positioned above the window 20 to direct radiant energy toward the wafer 12 and thus to heat it. In the Radiance reactor 10, the radiant heating apparatus includes a large number, 409 being an exemplary number, of high-intensity tungsten-halogen lamps 26 positioned in respective reflective hexagonal tubes 27 arranged in a close-packed array above the window 20. However, other radiant heating apparatus may be substituted. Generally, these involve resistive heating to quickly ramp up the temperature of the radiant source.
It is important to control the temperature across the wafer 12 to a closely defined temperature uniform across the wafer 12. One passive means of improving the uniformity includes a reflector 28 extending parallel to and over an area greater than the wafer 12 and facing the back side of the wafer 12. The reflector 28 efficiently reflects heat radiation emitted from the wafer 12 back toward the wafer 12. The spacing between the wafer 12 and the reflector 28 is preferably within the range of 3 to 9 mm, and the aspect ratio of the width to the thickness of the cavity is advantageously greater than 20. The reflector 28, which may be formed of a gold coating or multi-layer dielectric interference mirror, effectively forms a black-body cavity at the back of the wafer 12 that tends to distribute heat from warmer portions of the wafer 12 to cooler portions. In other embodiments, for example, as disclosed in U.S. patent applications Ser. No. 10/267,053, filed Oct. 7, 2002 and Ser. No. 10/280,660, filed Oct. 24, 2002, both incorporated herein by reference in their entireties, the reflector 28 may have a more irregular surface or have a black or other colored surface to more closely resemble a black-body wall. The black-body cavity is filled with a distribution, usually described in terms of a Planck distribution, of radiation corresponding to the temperature of the wafer 12 while the radiation from the lamps 26 has a distribution corresponding to the much higher temperature of the lamps 26. Preferably, the reflector 28 is deposited on a water-cooled base to heat sink excess radiation from the wafer, especially during cool down.
A kinetic means of improving the uniformity includes supporting the edge ring 14 on a rotatable cylinder 30 that is magnetically coupled to a rotatable flange 32 positioned outside the chamber. An unillustrated motor rotates the flange 32 and hence rotates the wafer about its center 34, which is also the centerline of the generally symmetric chamber.
An electrical means of improving the uniformity divides the lamps 26 into, for example, 15 zones arranged generally ring-like about the central axis 34. Control circuitry varies the voltage delivered to the lamps 26 in the different zones to thereby tailor the radial distribution of radiant energy. Dynamic control of the zoned heating is effected by, for example, 8 pyrometers 40 coupled through optical light pipes 42 positioned to face the back side of the wafer 12 through apertures in the reflector 28 to measure the temperature across a radius of the rotating wafer 12. The light pipes 42 may be formed of various structures including sapphire, metal, and silica fiber. A computerized controller 44 receives the outputs of the pyrometers 40 and accordingly controls the voltages supplied to the different rings of lamps 26 to thereby dynamically control the radiant heating intensity and pattern during the processing. Pyrometers generally measure light intensity in a narrow wavelength bandwidth of, for example, 40 nm in a range between about 700 to 1000 nm. The controller 44 or other instrumentation converts the light intensity to a temperature through the well known Planck distribution of the spectral distribution of light intensity radiating from a black-body held at that temperature. Pyrometry, however, is affected by the emissivity of the portion of the wafer 12 being scanned. Emissivity ε can vary between 1 for a black body to 0 for a perfect reflector and thus is an inverse measure of the reflectivity R=1−ε of the wafer back side. While the back surface of a wafer is typically uniform so that uniform emissivity is expected, the backside composition may vary depending upon prior processing. The pyrometry can be improved by further including a emissometer to optically probe the wafer to measure the emissivity or reflectance of the portion of the wafer it is facing in the relevant wavelength range and the control algorithm within the controller 44 to include the measured emissivity.
Bulk silicon representative of the wafer back side has an emissivity ε of about 0.7. In comparison, the front surface of a semiconductor wafer for integrated circuit (IC) manufacturing is subject to RTP while its front surface is composed of polysilicon and nitride portions. As a result, a typical front side emissivity is about 0.8 to 0.9. That is, the back side is more reflective than the front side.
Although the above temperature control has been effectively used to greatly improve the close and uniform control of temperature, increasingly difficult fabrication constraints necessitate yet further and tighter control. One of the difficulties is that the emissivity or absorption on the front side of the wafer greatly varies over the wafer's area. The non-uniformity arises from several origins. First, integrated circuits are invariably rectangularly shaped but arranged on a circular wafer. As illustrated in the plan view of FIG. 2, a large number of identical integrated circuit die 50 having rectangular shapes are arranged on the circular wafer 12. The arrangement of the die 50 avoids an edge exclusion zone 52 at the periphery of the wafer 12. The edge exclusion zone 52, typically having a width of about 2 mm, is felt to be unduly affected by edge effects such that any die 50 located within the edge exclusion zone 52 is highly likely to be defective or at least non-uniform relative to die 50 located closer to the wafer center. The die 50 are fundamentally patterned in a photographic process including for most advanced processing an optical stepper which successively projects a single image of the developing integrated circuit onto the area of one die 50 and is then stepped to another die to repeat the imaging process. Except for the stepper imaging, the remaining steps of the semiconductor fabrication process processes all die 50 simultaneously. At the end of processing, the die 50 are separated across kerfs 54 separating the die 50 to form separate integrated chips or circuits.
The temperature distribution in rapid thermal processing has been observed to depend upon the patterning of wafer and to vary from one level to another in the developing circuitry as well as between different IC structures. As a result of the rectangular die arrangement on a circular wafer, relatively large structured die regions 56 develop at several locations near the periphery of the wafer 12. These regions are not exposed to the stepper imaging. As a result, while the structured die regions 56 are processed along with the die 50, no pattern develops there. In contrast, as the multi-step and multi-level processing proceeds, the die 50 begin to develop a distinct pattern across the components of the developing integrated in which multiple layers produce a rapidly varying emissivity. On the dimensional scale of IC features, the emissivity variations can be averaged to an effective emissivity across the individual die 50. This effective emissivity, however, likely varies from the unpatterned emissivity of the structured die regions 56. An associated problem is that some of the internal die 50 may be used for test structures or patterns other than the production integrated circuits. These different die will have effective emissivities different than the production ICs. As a result, they absorb a different amount heat of heat than do the production ICs so that temperature uniformities arise near the test structures. A related problem arises from the kerfs 54 which must be kept wide enough for a saw but are generally unpatterned. As result, temperatures may vary near the kerfs. Similarly, if an IC has a distinct macro-pattern, such as RAM versus logic, the effective emissivities of the two areas may differ, producing temperature non-uniformities within the chip. It is possible that some areas of the die 50 develop a stack structure that acts as an interference filter for the high-temperature radiation from the lamps 26. These interference effects become more pronounced as higher-temperature lamps shift the radiation spectrum closer to film thicknesses. Even single layers of a different material may introduce significant reflection because of the abrupt change in refractive index.
A further problem is that the edge ring 14 may have a substantially higher emissivity than the structure developing on the wafer 12, which may be highly reflective. As a result, the edge ring 14 absorbs more radiation and heats to a higher temperature than the bulk of the wafer 12, resulting in the wafer 12 being hotter at its periphery than in its more central portions. This problem has been partially circumvented by tailoring the emissivity of the edge ring 14 by the use of coatings to more closely resemble the emissivity of the wafer. However, the wafer emissivity depends upon the IC design and the point in the fabrication process. Therefore, this solution in its extreme requires separate edge rings for each IC design and each step of the process, obviously an inconvenient and costly solution.
Aderhold et al. have addressed some of the problems with structure die regions 56 as well as some other macro non-uniformities in U.S. patent application, Ser. No. 10/243,383, filed Sep. 12, 2002. Their method electronically filters the pyrometer readings in those rings of the wafers exhibiting large circumferential temperature variations. Nonetheless, further improvements in uniformity in RTP are desired.